Referring to FIG. 1, a boost circuit of a dynamic-random-access memory (DRAM) device for driving word lines of the device is shown. A signal CLK1 is input into a delay circuit for turning on the refresh cycle of the DRAM device. The delay circuit transmits an output signal through an inverter 10 to connect to a precharge timing controlling circuit. Furthermore, the signal CLK1 simultaneously input into the precharge timing controlling circuit for preseting the precharge timing controlling circuit and the output signal from the delay circuit disables the precharge timing controlling circuit.
The capacitor C is charged by a precharge circuit when the delay circuit output signal to enable the precharge timing controlling circuit and the precharge circuit is controlled by the precharge timing controlling circuit. When the output signal from the delay circuit is transmitted from the inverter 10 to the precharge timing controlling circuit, the charging process of the capacitor C is stopped and then discharges to charge the word lines of the memory device.
Referring to FIG. 2, it shows a time sequence for operating the boost circuit in a DRAM device. The time sequence mentions the five voltage levels applying in the boost circuit in accordance to FIG. 1 and the five voltage levels includes VPP1, CLK1, A1, T1 and secO.
Still referring to FIG. 2, when signal CLK1 is high level on t1 time, the precharge timing controlling circuit is presented by CLK1 and T1 that is the signal CLK1 output from the delay circuit into the inverter 10, the inverter 11 and output from the inverter 12. The signal CLK1 is transmitted from the delay circuit, the inverter 10 to disable the precharge timing controlling circuit and the charging process of the capacitor C. That is, when A1 is low level on t2 time, the precharge timing controlling circuit is disable to turn off the charging process of the capacitor by using the precharge circuit. When the charging process of the capacitor is stopped as the outputting signal A1 is low level on t2 time, the capacitor C discharge to charge the word lines of the memory device. Only one section is selected in FIG. 2 shown, so the word line loading for the capacitor C to charge is only Cw where Cw is the capacitance of one unit word line loading.
In the charging process of the word lines in the memory device, the signal CLK1 goes low to enable the precharge timing controlling circuit since the signal A1 goes high on t3 time. When the precharge timing controlling circuit is enabled, the VPP1 is on precharge level for stopping the charging process of the word lines.
According to the above discuss, the boost circuit according to FIG. 1 just provides one kind of refresh mode which is 2k or 4k refresh mode,that is the loading is nonvariable. In the following descriptions, three U.S. patents, which describe the boost circuit in a memory device, is discussed.
Kaneko et al. discloses a semiconductor memory device in U.S. Pat. No. 5,587,958, which is filed on Dec. 27, 1994, entitled as "Semiconductor memory device including a boost potential generation circuit". Kaneko et al. describes a semiconductor integrated circuit device including a boost potential generation circuit and the boost potential generation circuit steadily generates a higher boost potential than an externally applied voltage. Moreover, the boosted potential generating apparatus includes a plurality of boosted potential generating circuits whose output terminal are connected in common, the plurality of boosted potential generating circuits are selected by a control apparatus so that the current supply capability is set in accordance with the number of word lines driven at a time.
Nagase discloses a semiconductor device in U.S. Pat. No. 5,373,475, which is filed on Aug. 6, 1992, entitled as "Semiconductor device in which the number of word lines selected simultaneously in a refresh mode is externally selectable and method of manufacturing the same". In this patent, Nagase mentions that a refresh mode switching signal generating circuit generates a refresh mode switching signal of an H level or an L level depending on whether a particular bonding pad is wire-bonded to a power supply terminal of a package. A refresh mode switching signal switches the refresh mode of a memory device according to the refresh mode switching signal.
Kim et al. filed a U.S. patent application, which is issued on Feb. 2, 1999 and whose Pat. No. is 5,867,442, on Dec. 19, 1996. The U.S. patent is entitled as "Variable output voltage booster circuits and methods". Kim et al. mentioned a method for controlling an internal booster power source in an integrated circuit memory device including a plurality of voltage booster active kickers.